1. Technical Field
The present invention relates to an active matrix substrate provided with a plurality of pixel electrodes in one pixel area and to a liquid crystal display device using such an active matrix substrate (pixel division system).
2. Background Art
In order to improve the viewing angle dependency of a gamma characteristic of a liquid crystal display device (for example, to control whitening problems of a screen), a liquid crystal display device that controls a plurality of subpixels provided in one pixel at different brightness to display a halftone by area gradation of the subpixels (pixel division system; see Patent Document 1, for example) has been proposed.
In an active matrix substrate described in Patent Document 1, as shown in FIG. 55, a pixel area is established between two adjacent gate bus lines 112; a pixel electrode 121a is arranged at an upper edge of the pixel area (a section adjacent to the gate bus line); a pixel electrode 121b is arranged in the middle thereof; a pixel electrode 121c is arranged at a lower edge thereof (a section adjacent to the next gate bus line); the pixel electrodes 121a, 121c are connected to a source-lead-out wiring 119 led out from a source electrode 116s of a transistor 116; a control electrode 118 connected to the source-lead-out wiring 119 overlaps the pixel electrode 121b via an insulating layer; and the middle pixel electrode 121b is capacitively coupled to the pixel electrodes 121a, 121c, respectively (capacitance coupling type pixel division system). In a liquid crystal display device using the above-mentioned active matrix substrate, each of subpixels corresponding to the pixel electrodes 121a, 121c can be designated as a bright subpixel, while a subpixel corresponding to the pixel electrode 121b can be designated as a dark subpixel. As a result, it becomes possible to display a halftone by area gradation of the aforementioned two bright subpixels and one dark subpixel. Here, as in the case of the pixel electrode 121b, a pixel electrode that is connected to (capacitively coupled to) pixel electrodes into which normal pixel data is written (in this example, the pixel electrodes 121a, 121c) and that becomes floating during normal writing is referred to as “pixel electrode in floating state” or “capacitance coupling electrode” in the present specification.
In the above-described liquid crystal display device using the capacitance coupling type pixel division system, it is known that a burn-in occurs at the subpixels including the pixel electrode 121b due to electric charges accumulated in the pixel electrode 121b that is capacitively coupled. This burn-in becomes particularly apparent when the pixel electrode 121b is arranged in the floating state.
Specifically, as shown in FIG. 56, a pixel electrode 61b is directly connected to a source line 55 via a transistor 56, and as the transistor 56 is turned on in every frame, the pixel electrode 61b and a data bus line 55 are electrically connected. Therefore, an electric charge accumulated in the pixel electrode 61b while the transistor 56 is off flows to the source line 55 when the transistor 56 is on. As a result, direct current voltage components rarely remain in the pixel electrode 61b, thereby making it unlikely that the burn-in occurs therein. On the other hand, in the pixel electrode 61a that is capacitively coupled to the pixel electrode 61b, an electric charge accumulated in the pixel electrode 61a remains even when the transistor 56 is turned on. Therefore, direct current voltage components remain in the pixel electrode 61a, which causes the burn-in to occur in the subpixels including the pixel electrode 61a. 
As a method to solve this burn-in issue, Patent Document 1 discloses a configuration of an active matrix substrate that supplies a Cs potential to a capacitively-coupled pixel electrode in floating state via a transistor connected to the gate line in the previous row. Specifically, as shown in FIG. 57, a pixel electrode 121b, which is in floating state and is capacitively coupled to a pixel electrode 121a, is connected to an auxiliary capacitance bus line 113 via a transistor 421 connected to the gate line of the previous row 112 (n−1). According to this configuration, transistors 421, 422 are turned on before a display voltage is applied to the subpixel electrodes 121a, 121c and to a control electrode 118 via a transistor 116, and the potential of the pixel electrodes 121a, 121c that are connected to the pixel electrode 121b and the transistor 116 becomes the same as the potential of the auxiliary capacitance bus line 113. Therefore, the electric charge accumulated in the pixel electrode 121b flows to the auxiliary capacitance bus line 113. As a result, it becomes possible to suppress the accumulation of electric charge in the pixel electrode in floating state, thereby preventing the occurrence of burn-in in the subpixels including the aforementioned pixel electrode.